1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. In particular, embodiments of the invention relate to a semiconductor memory device comprising a MOS transistor having a vertical channel structure.
2. Description of the Related Art
Conventional Metal-Oxide Semiconductor (MOS) transistors that each have a vertical channel structure can be arranged more densely (i.e., can be more densely integrated) than MOS transistors that each have a horizontal channel structure. Thus, techniques have been developed for fabricating a memory cell having a MOS transistor having a vertical channel structure for use in the fabrication of semiconductor memory devices having relatively high storage capacities and relatively high degrees of integration.
FIGS. 1A and 1B illustrate a conventional structure of dynamic memory cells each including a transistor having a vertical channel structure. Figure (FIG.) 1A is a perspective view of the conventional structure of dynamic memory cells, and FIG. 1B is a cross-sectional view of the structure illustrated in FIG. 1A taken along line X-X′.
The dynamic memory cells illustrated in FIGS. 1A and 1B comprise a P-type semiconductor substrate 10, cylindrical P-type channels 12 disposed on P-type semiconductor substrate 10 in a matrix and separated from one another, and N+-type gates 14 surrounding channels 12, respectively. The dynamic memory cells illustrated in FIGS. 1A and 1B further comprise N+-type drains 16 disposed under channels 12, respectively, and disposed, at least in part, between adjacent channels 12, wherein N+-type drains 16 disposed along a bit line direction are connected to one another. In addition, the dynamic memory cells still further comprise N+-type sources 18 formed on channels 12, respectively; word lines 22 surrounding N+-type gates 14, respectively, and connecting N+-type gates 14 that are adjacent to one another along a word line direction; cylindrical storage electrodes 24 disposed on and connected to sources 18, respectively; bar-shaped plate electrodes 26 insulated from and disposed partially in cylindrical storage electrodes 24; and a plate-shaped electrode 28 that makes contact with (i.e., commonly contacts) plate electrodes 26. Though it is not illustrated, N+-type drains 16 are used as bit lines.
The structure illustrated in FIGS. 1A and 1B is based on Korean Patent Publication No. 2006-41415.
FIG. 1C illustrates an equivalent circuit of the dynamic memory cell structure of FIGS. 1A and 1B. A memory cell MC including an NMOS transistor N and a capacitor C is disposed corresponding to each crossing of one of word lines WLi, WLi+1 and WLi+2 and one of bit lines BLi, BLi+1 and BLi+2. Each NMOS transistor N comprises a channel 12, a gate 14, a drain 16, and a source 18 (see FIGS. 1A and 1B). In addition, each capacitor C comprises a storage electrode 24 and a plate electrode 26 (see FIGS. 1A and 1B).
In each dynamic memory cell of the conventional memory device illustrated in FIGS. 1A, 1B, and 1C, since NMOS transistor N is formed having a vertical channel structure, and capacitor C is formed on NMOS transistor N, the memory device may have a higher degree of integration than a conventional semiconductor memory device including dynamic memory cells using a transistor having a horizontal channel structure.
FIG. 2 illustrates an arrangement of a conventional semiconductor memory device. The conventional memory device comprises a memory cell array 50, a column decoder 52, and a row decoder 54. Memory cell array 50 comprises sub memory cell arrays SMCA, sense amplifier blocks SA, sub word line drivers SWD, and junctions CJ. In addition, each sense amplifier block SA includes a precharge circuit P, and each sub word line driver SWD includes a driver D.
In FIG. 2, PX denotes a representative word line selection signal, NWL denotes a representative main word line signal, CSL denotes a representative column selection signal, WL denotes a representative word line, BL1 and BL1B denote a representative pair of bit lines having a folded bit line structure, and BL2 and BL2B denote a representative pair of bit lines having an open bit line structure. In practice, the folded bit line structure and open bit line structure illustrated in FIG. 2 are not used together in the same semiconductor memory device; however, they are illustrated together here for convenience.
Functions of the blocks illustrated in FIG. 2 will now be described. Sub memory cell array SMCA includes a memory cell MC connected between a word line WL and a bit line BL and stores data. Sense amplifier block SA amplifies data apparent on a bit line BL and data apparent on an inverted bit line (not illustrated). In addition, each sense amplifier block SA includes a precharge circuit P. When the bit lines have the folded bit line structure, bit line pair BL1 and BL1B of a corresponding sub memory cell array SMCA are each precharged by a respective precharge circuit P disposed at one side of the corresponding sub memory cell array SMCA. Likewise, when the bit lines have the open bit line structure in which bit line BL2 and inverted bit line BL2B for a bit line pair BL2 and BL2B, bit line BL2 corresponding to a first sub memory cell array SMCA is precharged by a precharge circuit P disposed at one side of the first sub memory cell array SMCA, and inverted bit line BL2B corresponding to a second sub memory cell array SMCA is precharged by precharge circuit P disposed at one side of the second sub memory cell array SMCA.
In addition, each sub word line driver SWD combines word line selection signal PX and main word line signal NWL to select a corresponding word line WL of the corresponding memory cell array SMCA. Junction CJ includes a driver (not illustrated) to drive word line selection signal PX. Column decoder 52 decodes a column address CA in response to a write signal WR and a read signal RD (which are not shown) and generates column selection signals CSL1 to CSLm (a generic column selection signal CSL is shown). Row decoder 14 decodes a first row address RA1 in response to an active signal ACT (not shown) and generates word line selection signal PX, and also decodes a second row address RA2 and generates main word line selection signal NWL.
FIG. 3 illustrates an arrangement of components of a sense amplifier block SA of FIG. 2. In particular, FIG. 3 illustrates an arrangement of a sense amplifier block SA of FIG. 2 having a rotated sense amplifier structure for k bit line pairs BL1, BL1B to BLk, BLkB (where k is a positive integer). Sense amplifier block SA comprises sub sense amplifiers SA1 to SAk and precharge circuits P1 to Pk, which are connected to bit line pairs BL1, BL1B to BLk, BLkB, respectively. Sense amplifier block SA also comprises column selection gates CSG, which, in FIG. 3, are respectively disposed at first and second sides of sense amplifier block SA. As illustrated in FIG. 3, sub sense amplifiers SA1 to SAk are disposed between column selection gates CSG and are divided into two groups of k/2 sub sense amplifiers. Sub sense amplifiers SA1 to SA(k/2) of a first group of sub sense amplifiers are disposed adjacent to one another along a first dimension, and sub sense amplifiers SA(k/2+1) to SAk are also disposed adjacent to one another along the first dimension. In addition, the sub sense amplifiers of the first group are disposed adjacent to the sub sense amplifiers of the second group along a second dimension orthogonal to the first dimension. Also, k/2 precharge circuits P1 to P(k/2) are disposed adjacent to k/2 sub sense amplifiers SA1 to SA(k/2) (i.e., the sub sense amplifiers of the first group), respectively, and another k/2 precharge circuits P(k/2+1) to Pk are disposed adjacent to another k/2 sub sense amplifiers SA(k/2+1) to SAk (i.e., the sub sense amplifiers of the second group), respectively. In addition, sub sense amplifiers SA1 to SAk are disposed between precharge circuits P1 to P(k/2) and precharge circuits P(k/2+1) and Pk. Each of precharge circuits P1 to Pk comprises three NMOS transistors (not illustrated).
When sense amplifier block SA of the conventional semiconductor memory device illustrated in FIG. 2 has a rotated sense amplifier structure, a first-dimensional length d of a region in which one of precharge circuits P1 to Pk (including three NMOS transistors) is disposed limits the amount by which a first-dimensional length of sense amplifier block SA may be reduced. That is, even though the first-dimensional length of each of sub sense amplifiers SA1 to SAk could be made smaller than first-dimensional length d, the first-dimensional length d of each region in which one of precharge circuits P1 to Pk is disposed limits reduction of the layout area of sense amplifier block SA. As used herein, a “first-dimensional” length is a length along the first dimension.
Also, when a memory cell using the NMOS transistor having the vertical channel structure illustrated in FIGS. 1A, 1B, and 1C is used in the conventional memory device illustrated in FIG. 2, parasitic components of the bit line and the word line grow larger, so operational characteristics of the device may deteriorate.
For example, as the parasitic components of bit line BL1 of FIG. 2 grow larger, it takes more time to precharge bit line BL1 to a precharge voltage level using the corresponding precharge circuit P of FIG. 2. And, as the parasitic components of word line WL grow larger, it takes more time to drive word line WL to a desirable level using sub word line driver D of FIG. 2. While the size of driver D may be increased in order to increase the ability of sub word line driver SWD to drive word line WL (i.e., to enhance drivability of the sub word line driver), increasing the size of driver D may not be a desirable solution because it increases the overall area of the device.
Thus, a new arrangement of components (i.e., structure) of a semiconductor memory device including a memory cell using an NMOS transistor having a vertical channel structure is required.